I'm trying to decide between the following two textbook comparators.  One is a clocked comparator design from Razavi, the other is a non-clocked design from Baker.

What are the pros/cons of each architecture?  I've listed what I can think of below.

Also, why in the Baker architecture is there a self-biased diff-amp in the output stage?  Why not a regular diff-amp with NMOS current src tail like in the pre-amp stage?
Thanks!

Hi jiesteve,

Bakker approach:
Pros: less offset and noise due to large input gain (the active loads can be made large and with low gm vs the latch devices which are typically large gm and small area). More gain also means less prop.  delay (important for some comparators).

This design can easily be converted into a clock comparator if M12 is clocked (and a few additional switches are added to guaranteed output state).
Biasing could be a normal one (I guess self biasing for saving area)

Razavi approach

Cons: more offset (due to lack of large input voltage gain and large gm of latch devices). More prop delay due to smaller gain.

Bottom line:
More power --> better noise and offset. This trade off is unavoidable.

Hope this helps
Tosei

For a high speed comparator, I think the pre-amp should have high gain but it is not necessary true for the following stages such as the latch or the intermediate stage. Because when the small difference is amplified by preamp it becomes a signal with relatively large amplitude, while the slew rate limitation prevails.