Hi,
      I am designing an analog charge-pump PLL with Ring Oscillator and i am kinda stuck at 1 point...
To start with-->
INTEGER PLL Specs :--
              Max Power Dissipation --> 3mW
              Osc Freq --> 1GHz
              Technology --> 65nm
              Loop Division Factor --> 1000
              Fref  -->  1 MHz
              VCO1 performance --> -43.11dBc @ 10kHz , -97.5 dBc @ 1MHz   -- @ 1mA current / 1.5 V supply
              VCO2 performance --> -60.11 dBc @ 10kHz, -114.4dBc @ 1MHz -- @ 5mA current / 1.5 V supply
              VCO2 performance is close to a LC Oscillator -- in almost all aspects other than area.

 The problem that i am facing is that because of low fref, i have to keep PLL bandwidth Low( <= 100kHz [Gardner's limit for CT approx.] )....At such Low BW coupled with high Loop Division Ratio, VCO Noise dominates both the in-band and out-of-band phase noise of the PLL & is making it violate the Noise Spec when i use VCO1 ...VCO2 however just satisfies the requirements with (that too with 100MHz/V VCO Gain --> difficult to get it in Ring Oscis but somehow i can achieve it) but exceeds my current spec....

Fractional PLL Specs :--    
              Max Power Dissipation --> 3mW
              Osc Freq --> 1GHz
              Technology --> 65nm
              Loop Division Factor --> 100  (reduced from 1000 to 100)
              Fref  -->  9.6 MHz (also increased)
              VCO1 performance --> -43.11dBc @ 10kHz , -97.5 dBc @ 1MHz   -- @ 1mA current / 1.5 V supply
              VCO2 performance --> -60.11 dBc @ 10kHz, -114.4dBc @ 1MHz -- @ 5mA current / 1.5 V supply
              VCO2 performance , i feel, is close to a LC Oscillator -- in almost all aspects other than area.
               S-D Modulator --->  20-bit , 4th Order MASH 2-2

         The problem that i face in fractional implementation is that even though Gardner's limit says PLL BW is relaxed upto 1MHz, but i am not able to enjoy that much BW, because S-D Modulator Quantization Noise starts dominating even the VCO1 Noise after say, 100 kHz...So i am back to 100kHz limit + quantization Noise of S-D Mod.

Need Help.....
Am i committing some mistake as in that these specs should be easy to achieve and i am stuck up unnecessarily &??
Is my VCO Design normal or bad ??

regards,
Mayank.