aaron_do
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Hi all,
For LNA input matching networks, it seems that the variation can be very high from simulation to measurement. For example, you need to match to some on-chip resistance. The most common ways i know to define the resistance are...
1. Common-gate architecture 2. resistive drain-gate feedback 3. An on-chip resistor 4. inductive degeneration
For 1. and 2., I can see that they can be matched to an off-chip resistor and perhaps can be quite accurate. However, for 3, the on-chip resistor can vary by up to 50% and in 4., the resistance depends on the biasing conditions, Ls and the process. I'm not exactly sure but I guess it can also vary by a similar amount. Apart from that, L and C can also vary on-chip. Does anybody have any comments on how to reduce the variation of such matching networks? Resistor trimming is not an option...
For a lot of commercial designs, i've seen that they don't bother to match to 50ohm, but simply quote the input impedance. Is this standard practice?
thanks, Aaron
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