Riad KACED
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Posts: 93
Swindon, UK
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Hi somisetty,
From your schematic, You could have launched ADE, setup the simulator to ams and then create a netlist. This would dump a module with a structural description of your design. All what you need afterwards is to create a verilog-A view for your cell and copy past the module. Simple as that ! Besides, this forum comes with tons of eaxmples, you may serach a bit as well.
BTW, the way you are adding the Power/Ground nets into your logic cells is UGLY. We usually do not do that. You can go with 2 approaches: 1. Have Power/Ground as implicit inherited connections in a schematic views 2. Explicit inherited pins on the Spectre view.
I would go for the latter approcah. Anyway, that was just a note ...
Cheers, Riad.
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