module inverter(vout, vde, vin, vss);inout vout;
electrical vout, vde, vin, vss;
input vde, vin, vss;

  analog begin

     vout_val = !(logic_in) ? vlogic_high : vlogic_low;

     V(vout) <+ transition( vout_val, tdel, trise, tfall);
  end
endmodule


module nand(vout, vde, vin1, vin2, vss);
inout vout;
electrical vout, vde, vin1, vin2, vss;
input vde, vin1, vin2, vss;

  analog begin

     vout_val = !(logic1 && logic2) ? vlogic_high : vlogic_low;

     V(vout) <+ transition( vout_val, tdel, trise, tfall);
  end
endmodule

module toplevel(v1, v2, vout_final)
how to instantiate above two modules in this module?
endmodule

Schematic is given below...

Hi somisetty,

What don't you try the solutions we have provided in your previous post ?
2. Why don't you serach a bit this form as there are tons of exmaple already there ? Look at http://www.designers-guide.org/Books/dg-vams/index.html for example.
3. Why don't you look at the verilog-AMS documentation which provided in your IUS stream ?

You need to help yourself a bit ...
BTW, the codes you have provided are noing going to pass the compiler I'm afraid ...

Cheers,
Riad.