somisetty
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module inverter(vout, vde, vin, vss);inout vout; electrical vout, vde, vin, vss; input vde, vin, vss;
analog begin
vout_val = !(logic_in) ? vlogic_high : vlogic_low;
V(vout) <+ transition( vout_val, tdel, trise, tfall); end endmodule
module nand(vout, vde, vin1, vin2, vss); inout vout; electrical vout, vde, vin1, vin2, vss; input vde, vin1, vin2, vss;
analog begin
vout_val = !(logic1 && logic2) ? vlogic_high : vlogic_low;
V(vout) <+ transition( vout_val, tdel, trise, tfall); end endmodule
module toplevel(v1, v2, vout_final) how to instantiate above two modules in this module? endmodule
Schematic is given below...
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