Hi all,
Can any one help me regarding VerilogA code for PISO block which is shown in below diagram?
Thanks inadvance

Thank you very much

Hi Somisetty,

I have never said there was any.
What I meant is given the few Verilog-A/verilog-AMS you have asked in this forum, you better take a look at the Book I have mentioned.
In other words, you better taked a week or 2 of your time, studying verilog-A and Verilog-ams languages. Once it is all clear in your mind, then you may start looking at the hundreds of examples in this forum.
You wouldn't expect people to write a tailored model for your very specific need, would you ?

Well, if you can't afford buying the book, which is fair enough, then You can look at either the Cadence's Manuals (I posted the links in a previous post) or the Accela LRMs. I can send the links if needed.

Regards,
Riad.