I looked at the plot. I see Ids mismatch decrease with increase in Vgs for a fixed W/L. But in your question you are saying "but after some voltage i feel device size would be very less and...". Can you be more clear on the question?

Ram

The plot is not at constant current. The label in the graph shows that it is for fixed W/L=20um/20um, Vdd=5V, Vsb=0V, Vto=0.85V.

ram

hi Jerry,
             you are correct man, but i came to industry very recently, here after running Monte i am not able to understand any result, so i am trying to learn some mismatch analysis. can you suggest any reference which will some estimation for present day process?

Thanks,
Rajasekhar.

Hello,
           I agree with ywguo as far as you consider only vds mismatch and ignore all other device mismatches....As vgs increases, delta Vt becomes a smaller proportion and hence mismatch improves...
  ...Considering device size mismatches, larger the device, larger the lengths, lesser the mismatches...
 ....These could be taken as general rules...

@ raja : As for mismatch, i monte-carlo the design over 200-300 runs & take 3-sigma or 5-sigma variation...

--mayank

@ rajdeep :

1 -->  Larger the device, lesser the mismatch....
2 -->  Larger the length, lesser the channel-length modulation effect, means larger the ro, so lesser the mismatch in ro coz of mismatch in farication of L....
3 -->  W/L ratio is governed by your ckt design, while mismatch dictates your Area, so since the ratio is fixed, you generally have to increase L. You can also change W/L ratio to improve mismatch and save on area but then you relax on some spec,say vgs/vds/ro of that particular MOS.

-->  Didnt understand the second para of your post   Quote:


 For same area, how can you increase both W & L ? One has to decrease to increase the other....
 For answer on W/L restrictions, see point 3.

--mayank

rajdeep wrote on Nov 18^th, 2009, 7:11am:


There is an important point you are missing here. The criteria for reducing mismatch depends on whether you are considering (1) a current mirror or a (2) diff pair

Just assuming threshold mismatches we have...

Case (1):

ΔI = I1-I2 ≈ gm ΔVTH (neglecting ΔVTH^2 term since it is supposed to be small)

Therefore current mismatch is proportional to gm.....proportional to W!!!. Definitely L is the one to be increased (and then increase W accordingly to keep the same gm as originally)

Case (2):
ΔVTH is directly "at the input" so here in principle is valid to increase either W or L (area at the end of the day). However, the diff pair load mismatches will create a ΔI that will be "reflected" to the input through the diff pair gm ---> we want large gm!!! -->
Input voltage offset is inversely proportional to gm

So in this case it is convenient to increase W (thus increase both area and gm)

Hope this helps
Tosei

Hi Tosei!

Spot on! Thanks a lot!

But isnt it, that in the case of a diff amp (i guess in every case), the gm of the input pair will be determined by the other specs (gain, ugb,noise)? That will fix the W/L. So any area increase to improve matching, can be done by increasing both W and L (since W/L is already fixed), in all practical situations of designing a diff amp. But I appreciate your point of view, as I myself asked, given a choice (as if W/L is not fixed) what is preferred . And I agree with you that in case of diff amp one would like to increase W, rather than L  for higher gm, quite opposite to what one would do in case of current mirror!!

Thanks again!
Rajdeep