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couragebo

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Can VerilogA code co-simulate with C or script languages?
Nov 21^st, 2009, 11:37am

Hi, everyone,

As you know, VerilogA is a very practical language for the circuit modeling. But in some cases it's not powerful enough, and it needs to "cooperate" with other tools, that's why I ask this question.

In fact, I'd like to create a VerilogA model in Spectre, in this model I need to do some complicated math calculation (like inverse of matrix, or multiplication of the complex number). This kind of job, since it's can be easily done by the existed code, I want it to be done outside the VerilogA module by some script language (Python...), and send back the results to the VerilogA module.

My question is: Is it possible that VerilogA code (in Spectre) calls some script functions? or are there some other methods can make this job done?

To my knowledge, there is a bridge between VerilogHDL and C, which is VPI, but can it be applied to VerilogA too? and Can Spectre support it now?

Thanks for your help.
Best regards
Bo

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rajdeep

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Re: Can VerilogA code co-simulate with C or script languages?
Reply #1 - Nov 23^rd, 2009, 1:23am

Hi,

You can do it with Verilog AMS. You can interface it with C, not sure of any scripting language.
You can download the Verilog AMS LRM and most probably chapter 10 talks abt it.

I have some exp of using it. But long time back and I remember that I used to run the design using ncvlog -ams option from command line. I guess it calls up sepectre (who else) to simulate the analog part, and a C function was used to write data (signal values) into a file (a named pipe to be precise). Im not sure what will happen if you use Spectre from Analog Environment!!

But it certainly works with Verilog AMS. You might have to move from Spectre....to AMS.

cheers!
Rajdeep

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couragebo

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Re: Can VerilogA code co-simulate with C or script languages?
Reply #2 - Nov 23^rd, 2009, 8:53am

Thank you, Rajdeep, for the quick reply and the in-depth explanation!

You are right, I probablely have move to AMS designer.

I read the latest LRM, but there is not an example in the manual. I guess that the C code should be compiled and put into the Verilog ams shared object directory, but i am not sure if it's correct or if there is any automatical method.

There are some handles that i can use to get the Verilog ams values, but I can not see how to link them to the C code, to be exact, how to create a simulator task and call the C code.

Rajdeep, can you remember some details about that? Thanks again.

Best regards
Bo

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rajdeep

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Re: Can VerilogA code co-simulate with C or script languages?
Reply #3 - Nov 24^th, 2009, 1:23am

Hi Bo!

Are you using cadence ICFB? Then you must be having the usual cadence directory distribution where it is installed. Now, I remember of using some of the makefiles from there!!! Yes!! and modified them to include my design library path etc. to make it run!!

I will try to dig it out from my old databse because it must be somewhere!! I should be able to share some of those files!! Meanwhile you can look into the cadence installation path to look for those makefiles!! :-D

cheers!
Rajdeep

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Frank Wiedmann

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Re: Can VerilogA code co-simulate with C or script languages?
Reply #4 - Nov 24^th, 2009, 1:26am

It is also possible to do a cosimulation with Spectre RF or AMS Designer and Matlab/Simulink. See http://www.mathworks.com/products/connections/product_detail/product_35807.html and http://www.cadence.com/rl/Resources/conference_papers/ctp_cdnliveemea2006_didier..., the chapter "Cosimulation with MATLAB and Simulink" of the Spectre RF User Guide and the chapter "Cosimulation with Simulink and AMS Designer" of the AMS Designer User Guide.

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couragebo

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Re: Can VerilogA code co-simulate with C or script languages?
Reply #5 - Nov 24^th, 2009, 6:39am

hi, Rajdeep, Thanks for your update.

I look into the cadence intallation path, and find many makefile, �they are in different path such as: ".../ic5141/tools/systemc/...", �"../ic5141/tools/itkDB", ".../ic5141/tools.lnx86/systemc/....". �After looking at my compile log file, i think it's the makefile in ".../ic5141/tools.lnx86/systemc/....".

In fact, I find also a GNUmakefile in the directory of the verilog module.

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« Last Edit: Nov 24^th, 2009, 8:44am by couragebo »

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couragebo

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Re: Can VerilogA code co-simulate with C or script languages?
Reply #6 - Nov 24^th, 2009, 6:53am

Thanks Frank for the sharing, it confirms that there exists a standard interface between AMS designer and the other simulators.

Also I did some search myself , and found an interesting book discussing the Verilog VPI or PLI interface:

"The Verilog PLI Handbook: A User's Guide and Comprehensive Reference on the Verilog Programming Language Interface "

http://www.amazon.com/Verilog-PLI-Handbook-Comprehensive-Programming/dp/07923848...

And there is also a paper about the Verilog / C co-simulation:

http://www.hindawi.com/journals/es/2008/171358.html

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couragebo

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Re: Can VerilogA code co-simulate with C or script languages?
Reply #7 - Nov 24^th, 2009, 8:42am

The following is makefile in the VerilogA directory:

Code:

# -*- mode: makefile -*-
# -*- eval: font-lock-fontify-buffer -*-

# Copyright (c) 2003 Cadence Design Systems, Inc. All rights reserved.
# This work may not be copied, modified, re-published, uploaded, executed, or
# distributed in any way, in any medium, whether in whole or in part, without
# prior written permission from Cadence Design Systems, Inc.

# Environment is supplied by ahdlcmicompile; this is just for convenience
ifndef AHDLCMI_ROOT
AHDLCMI_ROOT := $(shell cds_root spectre)
endif
ifndef AHDLCMI_PLATFORM
AHDLCMI_PLATFORM := $(shell cds_plat)
endif
ifndef AHDLCMI_TOOLS
AHDLCMI_TOOLS := $(AHDLCMI_ROOT)/tools.$(AHDLCMI_PLATFORM)
endif

# CONFIG_ROOT is the directory containing the GNUmake configuration files
AHDLCMI := $(AHDLCMI_TOOLS)/spectre/ahdlcmi
CONFIG_ROOT := $(AHDLCMI)/etc

# Standard variables for platform and compiler
include $(CONFIG_ROOT)/ahdlcmi.variables

# OBJDIR is the platform dependent object hierarchy.
OBJDIR := ./obj/$(AHDLCMI_SYSNAME)/$(AHDLCMI_OPTMODE)

# Make sure that all directories are created
dummy := $(shell [ -d $(OBJDIR) ] || $(MKDIR) $(OBJDIR))


default : all

# Ahdlcmi device library for ahdlcmi
SHLIB_NAME := ahdlcmi
DEVICELIST := ahdlcmidevicelist
SRCS := installdev.c $(foreach bdev, $(shell cat $(DEVICELIST)), $(bdev).c)
OBJS := $(addprefix $(OBJDIR)/, $(SRCS:.c=.o))

# Standard rules for platform and compiler
include $(CONFIG_ROOT)/ahdlcmi.rules

# Dependencies
$(OBJDIR)/installdev.o: $(AHDLCMI)/include/ahdlcmi.h
$(OBJDIR)/ha_res1.o: ha_res1_inst_static.h $(AHDLCMI)/include/ahdlcmi.h

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rajdeep

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Re: Can VerilogA code co-simulate with C or script languages?
Reply #8 - Nov 24^th, 2009, 2:06pm

Hi!

I have found the stuff!! There is a particular directory structure we used to follow, and there were altogether 3 makefiles placed in diffent hierarchry Undecided

We used ncsim. I know it doesnt help much...

Anyway, coming back to VPI calls. We wrote a task called mytestprog, and used to call it from the top level VerilogAMS module.
Code:

.....
initial
	$mytestprog($time);
always @(negedge clk)
	$mytestprog($time-1);
....

Pretty simple! Just like a system task! Now the next thing (rather the first thing) wud be to define this task somewhere and let ur simulator know there exists a task like that. This step is called registering your function. The directory that I was talking abt, there we found already such a function (c code) provided. This one was called vpiregn.c. (Im bit doubtful whether it was there already or we just edited it). But I think we just had to edit it!! Just here and there... It looks like this ..
Code:

extern int vpitest();

static s_vpi_systf_data systfTestList[] = {
  {vpiSysTask, 0, "$mytestprog", vpitest, 0,0,0},
  {0}
};

void setup_test_callbacks()
{
  s_cb_data cb_data_s;
  p_vpi_systf_data systf_data_p = &(systfTestList[0]);

  while (systf_data_p->type)
    {
	vpi_register_systf(systf_data_p++);
	if (vpi_chk_error(NULL))
	  {
	    vpi_printf("Error occured while setting up user %s\n",
			   "defined system tasks and functions.");
	    return;
	  }
    }
}

Now the next thing is to define the task which is the funtion vpitest(). So we wrote another C code to define vpitest(), where we used different VPI handles and functions.

In the manual you will get defintion of all these functions. Use them to write that all important C function of yours.

Hope this helps to give you a start...
Rajdeep

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couragebo Junior Member Offline Posts: 18	Re: Can VerilogA code co-simulate with C or script languages? Reply #9 - Nov 25^th, 2009, 1:56am hi, Rajdeep, Thanks a lot for the help and the typing... �:) The explanation is very clear and i know what i am going to do next. First I will create a very simple example and make it run... Thanks again Bo
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