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raja.cedt Senior Fellow Offline Posts: 1516 Germany	Clock buffer in PLL Nov 24^th, 2009, 6:06am hi, whenever PLL has to drive heavy loads, generally we keep clock buffers at the vco. Now the question in wehter to keep buffer in the loop or outside the loop? i feel in keeping in side the loop will increase the loop delay but buffer's noise will get high pass filtered. So can any one please explain this. Thanks, Rajasekhar.
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pancho_hideboo

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Re: Clock buffer in PLL
Reply #1 - Nov 24^th, 2009, 7:16am

I don't understand meaning of your situation and question.

But I put buffer out of loop.

If I include buffer into loop, loop will be largely affected by load of buffer and then make instable of loop or unlock of loop.
Also it is difficult to design proper loop filter.

[VCO]--[Buffer or �Power Splitter]---[Buffer]---[Freq Divider]--[PFD]--[CP]
� �|
� �---[Buffer]---[Load or Next Circuit to be drived]

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loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: Clock buffer in PLL Reply #2 - Nov 26^th, 2009, 4:44pm Fully differential PLL (talking ring oscillator here) with differential to single ended converter *outside* the VCO loop and then a feedback divider that is independent of the output buffering totally. Don't let the buffer system be any part of the PLL system. Get it far away. Jerry
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raja.cedt Senior Fellow Offline Posts: 1516 Germany	Re: Clock buffer in PLL Reply #3 - Nov 26^th, 2009, 10:45pm hi, so you are advising me to keep buffers outside of the loop, but all my buffer's all are adding lot of noise, so what i feel is if i keep buffers in side the loop, that will get filtered by loop. Thanks, Rajasekhar.
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pancho_hideboo Senior Fellow Offline Posts: 1424 Real Homeless	Re: Clock buffer in PLL Reply #4 - Nov 27^th, 2009, 4:38am raja.cedt wrote on Nov 26^th, 2009, 10:45pm: but all my buffer's all are adding lot of noise Which noise is dominant, PM or AM ?
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loose-electron

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Re: Clock buffer in PLL
Reply #5 - Nov 30^th, 2009, 9:25am

raja.cedt wrote on Nov 26^th, 2009, 10:45pm:

hi,
� �so you are advising me to keep buffers outside of the loop, but all my buffer's all are adding lot of noise, so what i feel is if i keep buffers �in side the loop, that will get filtered by loop.

Thanks,
Rajasekhar.

No, No, No - All of the noise within the bandwidth of the control loop will get reduced by the control loop. Considering the PLL tends to be low BW that is not going to help you a lot.

Actually pretty useless in my opinion, and I have designed a lot of PLL's

Start thinking about how switching noise in your environment is going to affect things. For ring oscillator PLL's your performance is going to be totally dominated by the interference/switching noise issues and not the inherent (thermal, flicker) noise issues.

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