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TSMC 0.18um I/O pads (Read 13926 times)
pgbackup
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TSMC 0.18um I/O pads
Dec 03rd, 2009, 1:49pm
 
I would like to learn a little bit about I/O pad design. To start off, I thought about designing a simple set (analog, gnd/vdd, in, out, in-out) pads for the TSMC 0.18 um process available through MOSIS. I am using Electric (http://www.staticfreesoft.com/) for this. I have AMI 0.5 um pads as a reference. If one takes a look at this document:

http://www.cse.psu.edu/~kyusun/class/cmpen411/09s/pj/AMI05Pad.pdf

one can see that the bonding pad (passivation layer) is 60x60 microns and the pitch between pads is 90 microns. Look at design rules for TSMC 0.18um at MOSIS (SCN6M_SUBM) for pads, I get this:

http://mosis.com/Technical/Designrules/scmos/scmos-glass.html

It says that pad design is process specific but gives general guidelines. My question is how do I figure out the size of the bonding pad? 60x60 micron on 0.18 will be double that on 0.35u.

If anyone has access or is using TSMC 0.18um I/O pads can they tell me the overall dimensions that would be reasonable? Or is there a way how I can determine this? Does size of I/O pads scale with technology? If so, I could possibly just use half the dimensions of those on the AMI 0.5 um pads?

Thanks for any ideas/help. Kind regards.
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Re: TSMC 0.18um I/O pads
Reply #1 - Apr 2nd, 2010, 8:58am
 
pgbackup,

There are two sources to get info. You can check with TSMC on what their bondpad recommendations are. In general, bonding technology doesn't scale directly with CMOS technology. Bond pads have gotten smaller over the years but this is not related to CMOS scaling - they are due to improvements in bonding machines and related technology. You can also contact the bonding house and look at their rules for minimum bond pad size. 60*60um was a good size in the beginning days of 0.18u but bonding houses may be able to do better than that today.
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