I would like to learn a little bit about I/O pad design. To start off, I thought about designing a simple set (analog, gnd/vdd, in, out, in-out) pads for the TSMC 0.18 um process available through MOSIS. I am using Electric (
http://www.staticfreesoft.com/) for this. I have AMI 0.5 um pads as a reference. If one takes a look at this document:
http://www.cse.psu.edu/~kyusun/class/cmpen411/09s/pj/AMI05Pad.pdfone can see that the bonding pad (passivation layer) is 60x60 microns and the pitch between pads is 90 microns. Look at design rules for TSMC 0.18um at MOSIS (SCN6M_SUBM) for pads, I get this:
http://mosis.com/Technical/Designrules/scmos/scmos-glass.htmlIt says that pad design is process specific but gives general guidelines. My question is how do I figure out the size of the bonding pad? 60x60 micron on 0.18 will be double that on 0.35u.
If anyone has access or is using TSMC 0.18um I/O pads can they tell me the overall dimensions that would be reasonable? Or is there a way how I can determine this? Does size of I/O pads scale with technology? If so, I could possibly just use half the dimensions of those on the AMI 0.5 um pads?
Thanks for any ideas/help. Kind regards.