When I use the transition filter to model a digital signal, it works nicely - as long as I use zero delay. If I put a non-zero number into the optional delay argument, the filter delays the transitions, but then completely ignores the options for rise and fall times. It appears that rise/fall time become shortened to one or two simulator steps, if delay is specified. Here is how I use it:

Code:

  V(q)  <+ transition( state ? vhi : vlo, 0, trise, tfall);
  V(qb) <+ transition( state ? vhi : vlo, delta_t, trise, tfall); 

The output of q rises and falls as specified, but the output of qb does not. Is this possibly a bug in HSPICE, or am I missing something?

Thanks, Bob

FYI, I'm using HSPICE version: C-2009.09 64-BIT
and Verilog-A Compiler Version 1.83.100.080509

Bob,

I faced the very same bug with hSpice64 2009.09. Going back to 2009.03 resolved this issue.

I am working with Synopsys AE on creating test-case for this bug, and therefore would like to more information about the netlist in which this bug occured. Please contact me.

Ari