i have designed two fully differential opamps using tower 0.18um 1.8v/3.3v technology (two stage, folded cascode + common source, with cascode compensation and continueous common feedback), one has dc gain of 108dB,
and the other has dc gain of 98dB (tt corner, pre-simulation); but after the layout extraction, when running layout post-simulation using calibre, i find that, the first opamp has dc gain of 69dB, and the second has only dc gain of 28dB, why?

in layout design, i have considered the basic layour design rules, such as matching of transistor pairs, wide enough wires for current density, the whole symmetric routing etc. i have tried to optimize my layout, but it only improves a little. i'm really confused.

has anyone ever met this problem before? and can anyone give me some advice or suggestion? what is the possible reason? pls help me.

my LVS is successful and there are no errors, but what is the reason for DC gain decreasing? which factors can cause the decreasing? thanks all.

Blue - sounds like something basic yet severe.
I agree check that you use the exact same PVT and setup.

Mayank - for 0.18um, I don't think STI, WPE are issues until 0.13 and smaller.

If it's truely parasitic related, there is an instability that changes the biasing and gain.  That is a LOT of DC gain which means there is a Hi-Z node that is very sensitive to C.


Wave

first, thanks all for reply. but when i run C+CC simulation, there is no parasitic res, the post-simulation is almost the same as pre-simulation. so, i think it is some parasitic res that causes the issue. however, i tried many ways to improve my layout, it doesn't improve at all. i'm really confused.
so i want to know, how to find which parasitic resistor causes the DC gain decreasing in post-simulation or in layout? are there some methods or ways? it's really very urgent, i really need your help. thanks all for reply. thanks. besides, i use the fully differential opamp for a sc circuit; when presimulation, the whole circuit resolution is 14bit, althrough the dc gain of opamp decreases a lot (from 98dB to 28dB)relative to pre-simulation, the whole circuit resolution for post-simulation can still be 11bit; why? i don't think this is reasonable. 28dB is only 25 times, i don't think the so small dc gain can make the whole circuit reach 11bit resolution in post-simulation. why? can anyone give me some suggestion, pls?
another point, when post-simulation, i find a zero in AC response curve, why? what's the reason? pls help me. thanks all.

anyone can help me?

Greetings,

1) Before running a parasitic back-annotated simulation, you might
   want to try running just an LPE, layout parameter extracted
   simulation. That is, you extract just the devices and simulate.
   --> This validate the layout is correct. You don't say much about
         the implementation, but it maybe that the folding and merging
         of devices has altered something.

  --> Basically your parasitic back-annotated capacitance simulations
        provide equivalent information so this appears to be done and
        the issue is not in the basic implementation.

2) There are two things(at least ) to look for in with back with
   back-annotated parasitics:
   a) Are the biases correct?
       If the bias currents are different than the performance will
       be different. An easy test is the power dissipation the both
       pre-layout and post-layout simulation results the same? After
       that check each stage for bias. Then check the common mode
       levels.
   b) If the bias voltages and current are okay and the performance
       is still off, then you need to look for other issues.
       - Can you probe internally and look at the output of the first
         stage? Are the results that same for both pre-layout and
         post-layout
       - Can you look at the gain of the second stage? Is the gain
          correct? You don't specify the implementation in detail,
          however, common-source amplifiers are sensitive to the
          resistance between the source and the power supply since
          this resistance can act like a degeneration resistor.
       - Can you look at the common-mode feedback amplifier?
         If it is not working properly the common-mode level may
         end up outside the optimum operating range?

   ---> You need to localize the issue, if possible. Localizing the issue
          can be difficult because everything is connected

3) Are you using ADE [IC5141/IC61] for your simulation environment?
   ADE has the option to back-annotate selected nets and simulate
   so you may be able to localize the issue?

4) Are you using ADE [IC61], using the Parasitic Aware Design flow,
   you can do sensitivity analysis to identify the relationship between
   specific parasitics and the dc gain.

5) You also mention a zero in the ac response. How is your
   compensation implemented? Is it possible that the zero
   is due to layout parasitic resistance in the routing for the
   comp cap? Or does the extracted capacitor include the
   extracted resistance of the plate? How was the compensation
  capacitor implemented, MOS CAP [MOS transistor]?

                                                                Best Regards,

                                                                  Sheldon

Here are some suggestions.
No matter how perfect the layout is, there is always some mismatch(of course, it's not the same thing with offset voltage) at the input of the opamp. Because of the large open loop gain, the output transistor may turn into saturation and the gain decrease.
You may try to extract the mismatch by connecting the opamp in the unit gain configuration, and substract the mismatch when you do open-loop AC simulation.

Of course you should make sure the mismatch is small enough, and I think it can be considered as  a part of the input offset voltage of the opamp.
Am I right? Any comments would be appreciated.

the  bias current in the 1st stage through the tail-current source is almost the same, any other reasons?