bobr
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Posts: 7
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When I use the bound_step() command in Verilog-A/HSPICE, it works as expected for timesteps of 2ps and above. When I try to force a timestep smaller than that, the simulator ignores it, and keeps the timestep at 2ps.
I've tried as many .option settings as I can find, and none seem to effect this limit. Using delmax is not an option, as I need the simulation to take longer steps at other parts in the sim, and only want to force the timestep small at key places.
I extracted the simplest example that displays the problem, and attached the files (an input HSPICE file, and Verilog-A module), in case anyone's interested. The Verilog-A code simply decreases the timestep by 10x from 1ns on down, and the result I see is that the minimum timestep stops decreasing at 2ps, even when bound_test() tries to force 1ps,0.1ps,... The output voltage of the module is equal to the timestep, so that you can observe the value that is being set.
Anyone know why this happens?
Thanks, Bob
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