Dear All,
              During lay out should we care about  uniformity of poly orientation in advanced process nodes like n40? If yes then what should be the major criteria to check out ?

  case 1 :  you can keep all your mosfets' gate along y direction and all the poly resistors along x direction. This will make sure the current flow through all the devices in x direction.

case 2 :  you keep both  mosfets' gate and poly resistors  along y then you have currents in mosfets (drain to sorce) in x direction but through resistors in y direction. But from uniformity of stress point of view case 2 will be better.


       Any thumb rule or standard practice regarding this issue ????

I agree with Jerry's comments.

Just consider different stress profiles in the package that will affect differently your poly res if they are placed in different directions.
Same happens with MOS and with other different gradients affecting your devices (temperature for example).

Best
Tosei

gate poly tends to be silicided. Usually 1-5 ohms/square

resistor poly is generally not silicided, and tends to be 50-300 ohms/square

(particulars depend on the foundry process of interest)

Now a question for those with TWO propellers on their Beanie Cap:

What's the differnece between a silicided process layer and a SALicided  process?

I will be truly impressed if you can answer this one without researching it.

Hi Jerry,
           
   I have come across the term "SALicide Process" and as far as i remember,it is usually used in poly layers making ohmic contacts like gate poly or routing poly.
    Precision Poly Resistors are usually mentioned as "SALicide blocked" in DRMs.
    At a contact / metal-Si Junction, metal layer reacts with poly-silicon to form a metal Silicide.
    And according to my memory, SALicide is just a name for a way of etching/laying out/lithographing this metal silicide on poly-silicon. Processed allowing such lithography are called SALicide processes.
       & Sorry, I forgot the full-form of the acronym 'SAL' in SALicide.

--
Mayank

LOL - Andrew went to Wikipedia...

A "silicide" is pretty well defined here:

http://en.wikipedia.org/wiki/Silicide

In a nutshell it is a class or grouping of chemical processes that involve silicon. Most chip designers think of it as a way to reduce the gate polysilicon resistance, but its actually a bit more than that.

A "SALicided process" is a little bit of a bastard - The original definition is an acronym that came out of IBM as a "Self Aligned Integrated Circuit Process"

The SALICided process came about when CMOS evolved away from metal gates, the gate poly was defined and the field oxide was defined, and those two items served as the alignment for the definition of the drain and source, which got diffused (nowadayus ion implanted) by using the gate poly and the field oxide as a mask for those D & S implants. which are done though the gate oxide.

It allowed the elimination of overlap regions and reduction of stray capacitance.

That and $ gets me coffee....

Jerry

Hi Jerry,

Interesting question. In some old processes, like Chartered 0.35um CMOS, there is a name polyside. I think that means only poly (including gate poly and resistor poly) is silicide. For SAlicide process, the poly and active area (drain and source) are silicide. The self alignment is done by the spacer at the edge of poly gate. The space is often made of oxide (including silicon dioxide and Nitride) which cannot become silicide. Am I right?


Best Regards,
Yawei

Like I said - the terms get scrambled up a lot and get used incorrectly.

Go read the above on Silicides, -  I have seen the term "polycide" (and other equally strange terms) used in various foundry documents as well. You need to go to the foundry to get the specifics of what they are really doing. In a lot of cases they made up a name for something they are doing, and that's fine. You invent it, you get to name it.

But then, here in the USA what gets created at Taco Bell (and their strange names) doesn't exist in Mexico.

Also, last I checked, the "Chinese Fortune Cookie" is very much an American invention and has nothing to do with China.

For those of you in the far east:
http://www.chinese-fortune-cookie.com/

Silicide? Salicide? Polycide? "Super Deep N-Well Trench Technology" and many other terms are used without a science basis and largely get created in the marketing department, not engineering.

Hi Guys,

I have another related question/comment. Keeping poly orientation for matching is clear.
But for advanced  processes (45nm and below) quite different transistor behavior (±20%) has been reported depending on the transistor orientation (related to the orientation of the crystal lattice of substrate).
Does anybody have experience in this area? Is that already checked by design rules in these technologies? DFM?

Cheers