i have designed a fully differential opamp (sc-opamp) with 2X function, but i have some problem here:
1, during sampling period, i set output vo+ and vo- to common level vcm (through switch), but the simulation results show that, they are not vcm, and one very high, one very low, i enlarge the switch size, but no improvement;
2, the two inner input node of opamp has a big difference between sampling and holding phase, in sampling phase, i set them to vcm through switch, but in holding phase, the voltage of the two inner input node of opamp has a decrease of 200mv or so, why?
3, when running post-simulation, i found that, the transcient differential output in the first period is larger or smaller than the normal voltage, for ex: when the differential input is 700mv, the differential output should be 1400mv, but the transcient differential output in the first clock period is not 1400mv, is 1450mv or so, and after the second period, it becomes normal, 1399mv or so. (i use dc source for input signal)it is very strange, why?
someone tell me, it is because the mismatch of parasitic capacitor, but why? how to find which parasitic cap cause the problem, or any other reasons?

pls help me,thanks for your reply.thanks.