The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Apr 29th, 2024, 11:48am
Pages: 1
Send Topic Print
about PLL direct simulation (Read 5758 times)
Chris Yang
New Member
*
Offline



Posts: 8

about PLL direct simulation
Jan 04th, 2010, 3:29am
 
Dear All,

I am designing a PLL now.
I can run the VCO phase noise simulation, and got an acceptable result.
I want to see the overall phase noise performance of PLL.
So, I run the same simulation for PLL.
But the simulation always fails.
Cadence says the memory is insufficient, when pss is finished and pnoise is just started.
Sometime, the simulation can not converge when pss is running.

Is the direct PLL Pnoise simulation feasible?

Please help me~~~~~~~   Cry
Back to top
 
 
View Profile   IP Logged
pancho_hideboo
Senior Fellow
******
Offline



Posts: 1424
Real Homeless
Re: about PLL direct simulation
Reply #1 - Jan 4th, 2010, 6:50am
 
Chris Yang wrote on Jan 4th, 2010, 3:29am:
Is the direct PLL Pnoise simulation feasible?
Is your PLL "Integer N PLL" ?
If so, evaluation of phase noise by pnoise is possible ideally.
But we very often encounter convergence problem actualy if we adopt Cadence Spectre.

If you can not get convergence using Cadence Spectre, try to use Agilent GoldenGate simualtor or Berkeley DA's RF FastSpice.
Agilent GoldenGate simulator have special analysis for PLL based on steady state analysis.
Back to top
 
 
View Profile WWW Top+Secret Top+Secret   IP Logged
sheldon
Community Fellow
*****
Offline



Posts: 751

Re: about PLL direct simulation
Reply #2 - Jan 4th, 2010, 7:53am
 
Chris,

  Performing PNOISE analysis requires a Periodic Steady-State
operating point. There are some points to consider:
1) Fractional-N PLL do not have periodic steady-state operating
   points so PSS/PNOISE can not be used
2) Finding the Periodic Steady-State of an Integer-N PLL is
   possible if the divide ratio is low
   --> I have simulated with divide rations of up to ~50
3) You will probably need to use the 64 bit executable
    --> I have found that this usually resolves the out of memory
          problem  
4) You should probably not save the transient data for the tstab
   and use the save selected to manage the amount of data
   stored
5) You probably need to use a longer stabilization time than the
   typically recommended, the PLL should basically be locked
6) I have used both the Shooting Newton and Harmonic Balance
   solvers to simulate the periodic steady-state
7) If you use the Shooting Newton solver, use it with APS-RF

  One other option to consider, is using the Noise-Aware PLL flow.
It will allow you to analyze noise to the block level quickly. While
the flow uses behavioral models, the behavioral model creation
has been automated.

                                                        Best Regards,

                                                           Sheldon
Back to top
 
 
View Profile   IP Logged
Mayank
Community Fellow
*****
Offline



Posts: 334

Re: about PLL direct simulation
Reply #3 - Jan 4th, 2010, 11:23am
 
Hi,

Simulating PLL phase noise through PSS is tough....Huge cktry with lots of transistors makes it difficult for pss to converge as pss finds convergence at every node & net of the ckt....Best way is to use SpectreRF's Noise Aware PLL Macro Model.....There you just run a long transient which doesnt take much time coz it is running on behavioural models, and use Plot PLL Phase Noise option of Direct Plot Form.

--
Mayank.
Back to top
 
 
View Profile   IP Logged
Chris Yang
New Member
*
Offline



Posts: 8

Re: about PLL direct simulation
Reply #4 - Jan 4th, 2010, 11:23pm
 
Dear All,

Thanks for your kindly reply.
I will try these solutions just mentioned.
Thank you very much!!

Chris   Smiley
Back to top
 
 
View Profile   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.