lhlbluesky_lhl
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have designed a SH(sample-holde) circuit, just as the picture shows (fig1). it consisits of four TG and two Buffer, IN is a changing signal, first, S1 is on, and IN is stored in C1 (just called IN1), then, S2 is on, IN (has changed) is stored in C2 (IN2). after a while, S3,S4 on at the same time, readout the difference of IN1 and IN2 (fig2). that is, S3 and S4 are the same signal.
originally, i use S3 and S4 for different ports in layout, and i add stimilus in the four ports, of course, S3 and S4 have the same stimilus, S3- and S4- have the same stimilus, and the simulation result is ok (12 bit resolution). while i want to connect S3 and s4, S3- and S4- together separately in layout, so only two ports needed. however, when rerun the simulation, the result is very bad, very different, only 8 bit resolution.
i'm sure that, i only connect them together in layout with a short wire (fig3), nothing else. but why? why does the resolution have such a big reduction? i cheched my layout, except the two connecting wire, no other change has made. but the simulation result is very strange, can any one help me? thanks all.
in fig3, only two stimilus added, one for S3(S4), one for S3-(S4-). i really need your help, thanks.
and after i connect S3 and S4, S3- and S4-, the simulation result shows that, the resolution decline starts at the node after the first switch (that is, the positive end of buffer), but i have not changed that part, i only added the two short wire as fig3 shows. it is very strange, why?
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