what is the advantage/disadvantage of using  a self biased opamp ?

this structure shown in the fig is  commonly used as an error amp in the bandgap voltage ref circuits, but this self biasing adds one more positive feedback  (which complicates the stabilty). So is there any major reason/advantage for using self bias in terms of systematic offset/temperature dependence??

regards,
yvkrishna

@vamis: eventhough it is a self bias circuit that doesn't mean it complicates stability (i am assuming that you are using this opamp for some other purpose, so that if you keep your main loopgain keep the ckt functions properly)howerver this +ve feedback gives startup troubles some time. Comming to the importance of the circuit  it is mainly to track the system poles with load current and it will give higher dc gain also. But can you please tell me why N$ is nmos, i guess it is Pmos.

@rf: I agree with you for supply dependent bias current, but due self bias it will operate at desired oparating point and could you please ecplain 2nd half of your post.

Thanks,
Rajasekhar.

hi mayank,
               it is a replica based self bias, so N4 is mainly to replicate pmos diff pair transistor, so i guess it should be pmos and gate may go to ground.

Thanks,
Rajasekhar.

Thanks for the replies guys.

I agree with mayank, the presence of nmos if just to create some vds drop there.. at the same time as raja questioned pmos would have been more suitable there.
Just to confirm are you guys pointing out the presence of nmos/pmos would help in reducing the systematic offset ??

@rf-design
as mayank pointed out i feel N3 should not be in linear

also since loop is positive one,its loopgain should have been <1 to avoid unstabilty.
please clarify about the statement:
""To get a bias current higher than zero the current loop gain should be higher than 1. So the bias current is set when the gain is equal to 1""


@mayank
just out of curiosity ..Is it fine if we can make the total loop gain of the system negative (assume a bandgap ckt with other loops +ve and -ve)  even with the loopgain of this selfbias loop >1;


Guys finally I have a doubt about placement of additional pole in this self bias loop ..(taking into account of the startup/stabilty...)
will this pole be present exactly at the same location the total transfer function?? (assume this opamp is used in a bandgap circuit)
so is it just enough to place this place from loop's UGBW for sufficient phase margin??

I have this  question because I observed problems with startup while simulating in which i havent took care of this pole location...


many thanks for your suggestions/comments.

regards,
yvkrishna