Hi,
@ raja : Quote:But can you please tell me why N$ is nmos, i guess it is Pmos.
I guess you meant 4 by the $....& no, N4 is supposed to be a nMOS only...It's gate is connected to vdd as it's supposed to operate as a resistor in linear region...
Quote: I agree with you for supply dependent bias current, but due self bias it will operate at desired oparating point
That desired operating point will change with change in supply voltage...and you usually dont want that...that's why this kind of biasing in not so sought after...
@ rf-design : Quote:So only if N3 goes into LIN mode the bias current is defined
No, i Guess not....If N3 goes into Linear, the whole funda of self-biasing is gone....
The diode connected nmos load N2 generates N3's bias, which in turn generates P3's bias, which is mirrored back into Tail Current Source P0.
To get a bias current higher than zero the current loop gain should be higher than 1 The Loop's a +ve feedback one....If the loop gain, be it current or voltage, is higher than 1, it would be unstable....A Startup ckt is needed to avoid 0 Bias Current meta-stable condition.
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Mayank.