AmiyaB
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Posts: 8
Kolkata
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I have simulated the verilog-A code for and-gate using spectre simulator. I have stopped the simulator using the statement : kill USR2 <PID> from terminal. I got the saved state file (*.srf). When I started the simulation again from the same point (where i have stopped) using the spectre recover statement, it is showing that the simulation is running. # spectre +lqt 0 tb.scs +recover=tb_recov.srf_10us But the results are not correct.
The code for AND gate and its test bench, what i have used are given below.
Can You tell how to re-simulate it properly. ------ AND gate code ============ `include "constants.vams" `include "disciplines.vams"
module andgate (y, a, b, vdd, gnd); input a, b; output y; inout vdd, gnd; electrical a, b, y, vdd, gnd;
parameter real tr = 10f, tf = 10f, td = 10f; real y_val, vd, gn, vt; integer logic1, logic2;
analog begin vt = 0.5 * V(vdd); vd = V(vdd); gn = V(gnd); logic1 = (V(a) >= vt); logic2 = (V(b) >= vt); y_val = (logic1 && logic2) ? vd : gn; V(y) <+ transition(y_val, td, tr, tf);
end endmodule
Test bench ========= V1 (VSS 0) vsource dc=0 type=dc V0 (VDD 0) vsource dc=1.8 type=dc I0 (Y VDD B VDD VSS) andgate
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