Hi. I'm designing driver of 1.65Gbps TX for display chip.
The attached picture is driver of TX.
Id=12mA, Rtx=50ohm is given and PMOS input tr size=100u/0.1u ,
load PMOS tr. size =240u/0.4 is selected in my design of 90n tech.

I am do timing simulation with TX driver + 1/2 size same type pre-driver+load condition and check the waveform at Rx, but i am concerned about the simulation coverage.

How am i optimize the CML buffer and what should I do for robust design?