Hi,
     I am trying to simulate a PLL with transient noise enabled...
Also i am placing a 10mV white noise source on VDD.....through a verilogA model using $rdit_normal() function.
I have modelled supply inductance + interconnect resistance through a small, finite-Q inductance.

 White Noise source works properly.....But the ckt simulation time increased a LOT !!! around 1ps / sec.  
Can't simulate this way......Are there any better methods to simulate transient noise with a noisy supply ???

--regards,
Mayank.