The proposed architecture is not a AB-Mode differential output stage. Furtheron the second current mirror stage with a ratio "n" is to some degree redundant. You can instead made a direct connnection of the first current mirror stage to the output with a mirror ratio "n". The next issue is that the common mode current of the input stage is not defined and could not be derived from the common mode output. That is because if you change the common mode voltage level of the differential input stage you only change the bias level in the mirror stages. So a second common mode stabilization stage is needed for the differential input stage.

Most AB-architectures use the principle of square law current of MOS devices. Then two devices are combined which have a complementary linear voltage drive of the two devices. Next you do not want to cut off a current complete because it takes then more time to charge the gate voltage to recover to the active operating region. So some circuit tricks set a minimum current to the AB-mode control.

The biggest issue is that the transconductance of the output stage define with the maximum output capacitance the critical parasitic pole. So the unity gain bandwidth could not be higher than this value. So if the bias current in the output stage varies you have to compensate for the minimum or quiet operating point. So the unity gain bandwidth is reduced to the A-mode amplifier by the the amount of AB-current ratio.

Thanks for good comments,

If I've understood right, the reason that this may be a class AB stage is that the PMOS current of one output is a copy of the NMOS current of the other output. And, moreover, the peak output current can be order(s) of magnitude larger than the quiescent current set by the two output-stage current sources.

About CM control, I guess there are several ways to introduce that. But one issue in a fully-differential output stage is that the CM voltage INTO it should excite CM current OUT of it, which would not be the case if the first current mirror in the output stage is removed. But I'm sure there may be other (better?) ways to introduce CM output control than to connect the CM-regulator output to the diff-input-stage bias-current generator.

There may be a recovery time after one output PMOS (and the other output's NMOS) has been fully turned off, i.e., after returning from a large class-B output-current excitation. I suppose this schematic is a simplified one when it comes to such details, and therefore some minimum-bias current source needs to be added, as you say.

To set GBW, I had hoped that Cc could provide enough local feedback, on at least one output at a time (in class B operation), giving GBW=~Gm,diff/Cc. But that I've not yet checked how reliable it is also when it comes to manuf/temp spreads.

About literature, I've read quite a few papers in which many stages give very large gain spreads, e.g. depending strongly on the load impedance, and some of them don't even guarantee thermal stability inherently, depending on implementation technology (CMOS/Bipolar). But I just might haven't found the right papers yet maybe.

Again, thanks for pointing out several critical issues, and more comments are of course very welcome!

Regards,

Carl F