Hi,
Can any body give me an example digital/analog ckt where the zero bias (Vgs=0) gate capacitance (Cgg) is critical?.

I see some of the digital blocks like ring oscillators and standard cells where load cap changes matters, but I think inversion capacitance plays dominant role there.

Thanks

When Vgs=0, the device is off and the gate capacitance is a combination of oxide cap in series with depletion cap and overlap cap. This value is low (approx half) compared to gate capacitance at Vgs=Vcc, which is inversion capacitance (approx equal to oxide cap).

My question is, is there any circuit that heavily depends on FET zero bias capacitance?

Thanks