manikandan wrote on Feb 13th, 2010, 4:56am:am new to verilog a and cadence..
What do you mean by "
cadence" ?
The followings are general notes for you.
- Always describe vendor's name which you use as tool or simulator.
- Don't do multiple posts which are same content.
-
Don't request source code or behavioral model without any efforts.- There are many simulators which have analyses called as PSS, PAC and Pnoise.
-
Describe in detail with using correct terminologies.- Warnigns are different from Errors.
- ADS is not name of simulator.
-
There is no tool which name is Cadence.- Don't use Direct Plot of Cadence ADE blindly without knowing definition.
- All gains in Direct Plot of Cadence ADE are "right", "true" and "practical" voltage gain.
- Don't mix up Simulation with Post Processing. They are completely different phase.
- MATLAB are different from Simulink.
- Learn measurements using actual instruments. Not "EDA Tool Play
manikandan wrote on Feb 13th, 2010, 4:56am:i didnt get the output wave which should actually remain high for 40 input clocks..help pls..
I can't understand what you mean by "
actually remain high for 40 input clocks".
If output wave is high during 40 input clocks, divide ratio is 80 not 40.
And before arguing output wave, there are syntax errors and many incompletenessed in your Verilog-A code.
Do you truely run this Verilog-A code.
manikandan wrote on Feb 13th, 2010, 4:56am:module bitcounter(clkout,clk,reset);
output clkout;
electrical clkout;M
input clk;
electrical clk;
input reset;
electrical reset;
parameter real vlogic_high=3.3;
parameter real vlogic_low=0;
parameter real vtrans_clk=1.65;
parameter real vtrans_reset=1.65;
parameter real tdel=60p;
parameter real trise=100p;
parameter real tfall=100p;
integer reset_flag;
integer count;
integer d[0:5];
integer i;
analog begin
@ (cross(v(clk)-vtrans_clk, +1)) begin
if(v(reset) < vtrans_reset) begin
if (d[3]&&d[5]) begin // is this correct?
reset_flag = 1;
count=0;
end
end
else
reset_flag=0;
for(i=0;i<=5;i=i+1) begin
count=count+1;
end
end
v(clkout) <+ transition (vlogic_high*d[5]*d[3]*!reset_flag, tdel, trise, tfall);
end
endmodule
//is this a correct approach?
Do you think so?
First, there is no definition for d[3] and d[5]. How do you define "d[0:5]" ?
Remake verilog-A code after studying the following.
http://www.designers-guide.org/VerilogAMS/functional-blocks/freq-divider/freq-di...