[quote author=pancho_hideboo link=1266231079/0#13 date=1266482886]Manas wrote on Feb 17^th, 2010, 9:52pm:
Not correct.

First, Vx is a floating node. So Qx can not be removed.
Second, it could result in stagnated bias points. So OP Amp can't work correctly.

Manas wrote on Feb 17^th, 2010, 9:52pm:
Not correct.

C1, C2 and Cx share Qx in initial state.
Qx is not charged in only small Cx.
So after restribution of charge, I can't expect Vx correctly.


If feedback networks are composed of only capacitor,
  - It is difficult to fix DC bias points properly.
    It could results in extreme bias points, e.g. all devices are saturated or cut off.
    This is very true for CMOS OP Amp.
  - No feedback effect at DC and low frequency. It could cause unstability.

If feedback networks are composed of only resistor,
  - It could be unstable for high frequency.

SORRY,
I AM WRONG. AS IT IS A FLOATING NODE, THE Qx CHARGE CAN'T BE REMOVED. HENCE THAT POINT CAN'T HAVE DESIRED VOLTAGE DUE TO OPAMP ACTION.
SORRY AGAIN FOR THE WRONG INTERPRETATION.
AGAIN THANKS A LOT !!

But unstability issue never can be resolved even if you implement
startup circuit with feedback networks compopsed of only capacitor.
[/quote]

Thanks A Lot !!
Can u provide  any example or cases where the above mentioned issue has happened or the designers have faced the problems??
You may point to any reference paper or material..

This is Just for Completion of the Discussion of the POST. I have attached the desired files

Manas wrote on Feb 22^nd, 2010, 1:52am:

pancho_hideboo wrote on Feb 22^nd, 2010, 2:03am:

Of-Course due to Load Capacitance the Phase of the Stand-Alone OPAMP phase degrades even if there is resistive feed-back or not ( is a lose statement. It may improves the stability).

If I break the loop at the o/p node of the OPAMP and apply a Vtest at the break point  then the Resistors and the i/p cap forms a Low-pass filter and adds a effective pole in the LOOP-gain as the Feed-back ressistors are kept quite high for not reducing (loading) OPMAP o/p resistance.

I wonder how due to the resistive feed-back and  the load capacitance the  pole is added in the Loop-gain. Putting the my doubt i other way--> How resistive feed-back degrades the pole caused by the load Capacitor