Hi,

Facing strange issue on silicon for opamp in Sink Current test at lower temperature(-40degC & -60degC) & @ VCC=2.7V. But this problem doesn't exist forVCC=2.5 & 3V.

Main culprit for the issue is Node_S variation(marked in attached figure). But the variation at the specified node is due to which effect is not able to understand.

Would like to know why this happening on silicon ?. The test results and schematic and test set up is attached. But this behaviour is not observed in simulation at any condition.

waiting for responses........
thanks

regards,
analog_chip