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Assura LVS Extracted View (no parasitics) and Substrate extraction (Read 603 times)
alanlcit
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Assura LVS Extracted View (no parasitics) and Substrate extraction
Mar 04th, 2010, 11:48am
 
A couple of questions:

It used to be possible to get Assura RCX to extract just an "LVS Extracted" view.   Perhaps because we upgraded to a newer version of (Assura 3.2 USR2 HF11), this option is no longer available from the drop down list on the first page of the RCX form.    Is there some way to manually include this option in the rsf so that it excludes all parasitics from the extracted view?

It is sometimes useful to just be able to verify that the extracted view simulates the same (at least DC-wise) as the schematic view, without the overhead of added components.   That's the motivation here.

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Second Assura issue:    We are using TSMC 0.18um process.    When generating extracted views, we found something horrifying:   All the NW and RW (substrate inside DNW) and SUB nodes are treated as dead shorts to one another!!!    This means that when running an R extraction, current in the various supply buses is NOT correct (because there is often an alternate "shorted" path via the substrate or NW, etc.).    This is awful.

What is the Assura tool which will allow us to properly extract resistance of the substrate?   And how much work is it to support this tool?   We have heard that special files are required from the foundry, but if they are simple enough to generate, perhaps we can generate them ourselves.     We really just need an approximation to the correct resistance of the substrate - something that is NOT a dead short.   This will allow electromigration simulations and such to provide us with reasonably accurate results.    

As a stop gap measure, we've modified the extraction deck and proc file to extract contacts to NW and SUB separately, and model them as having a lot more resistance than they actually do.   This gives us close to what we want, but it's still not great because it results in poor local ties of the NW/SUB on ALL devices.   Probably ok for DC simulations for electromigration (as long as current through forward biased wells/substrate connections was not relied upon for circuit operation), but if any higher frequency simulation was done, it might not give great results due to poor ties of the local substrates.

So we're looking for something better.  

Appreciate any help on these issues!

Alan
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Tatyana Gordeeva
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Re: Assura LVS Extracted View (no parasitics) and Substrate extraction
Reply #1 - Mar 22nd, 2010, 7:18am
 
Hi Alan,

"LVS extracted" view is available in all Assura versions. However there is a UI template setting file that can disable certain options appearing in GUI. Please double check if LVS extracted view is disabled in the template file. You can look at .rcx_setup.tpl file or see it via GUI: Assura -> Setup -> Rcx Setup...

As for the substrate short issue, there are multiple solutions. Please check either ?ignoreVia option at run time, or stamp=1 or stamp=2 settings at p2lvsfile. However the best solution in this case will be migration from RCX to QRC (where QRC can consume same RCX techfile and command file for easy migration). Starting from QRC EXT91 release, lots of substrate shorting issues are automatically been taken care by the software without user specifying ?ignoreVia.

Best regards,
Tatyana.
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