thank you all!
I found that the bulk switching technique is not very good, because this technique just promote a little of the performance.
the biggest problem with the CMOS switch (or TG) is the parasitic cap, which contribute to the input capacitance of the ADC. for example, the parasitic cap of a CMOS switch is 200fF while the correponding sampling cap is just 100 fF. So with 25.6 pF samling cap (determined by KT/C noise), the corresponding parasitic cap is about 50 pf, then the total input cap is about 75 pF!
Normally, the input cap is just 30 pF in the company product datasheet of the 16 bit or higher resolutio ADCs. It really confuses me. How to realize it? can anyone give me some suggestion?
loose-electron wrote on Mar 15th, 2010, 3:00pm:if you are switching a binary weighted capacitor array in a dynamic manner you may want to consider some alternative architectures.
Hi, loose-electron
Can you give me some advices? thank you!