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swolf

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Re: PMOS switch bulk connection
Reply #15 - Jun 30^th, 2010, 2:44am

hi, Mayank, thank you for your reply.
the LSB CAP with the size of one unit cap (100fF) needs a CMOS switch of a specific size, whose parasitic cap is 200fF; the second weighted CAP with the size of two unit cap needs two such CMOS switches to keep the linearity, so the parasitic cap is doubled.
That is, 100fF Sampling Cap corresponds to 200fF parasitic cap.

hi, Berti
I adopted this technique in pipeline ADC. But ...
Initially, I didn't want to use bootstrap switch here because there are so many switches. Now, it seems that I have to use this technique.
But I am still not very sure about it. Do you ever use this technique in this situation? any suggestion? Thank you.

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Asmodeus

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Re: PMOS switch bulk connection
Reply #16 - Jun 30^th, 2010, 4:17am

From the above discussions, i guess u r sampling the input at the bottom plate of the DAC.

Are u using any buffer to drive the DAC ?? If not that could be an issue here. A rail-2-rail sample and hold usually needa a buffer to drive large DAC. Parasitic capacitance is not a big issue in the design of SAR ADCs, if it doesn't take part in charge redistribution.

Then 200fF parasitic capacitance seems a very big number for me for 100fF capacitance to settle in 1us. I will really ask you to look into the numbers once again

Which technology node r u using ??

U can also design switch taking into consideration the effect parasitics added by it into settling consideration. Just make sure accessible node of parasitic capacitance is always at ac ground during charge redistribution. All u need to worry about is driving this total capacitance during sampling operation which will ask for a buffer.

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~VJ~

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swolf

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Re: PMOS switch bulk connection
Reply #17 - Jun 30^th, 2010, 8:25am

Hi, Asmodeus
yes, I used the bottom plate sampling technique.

About the CMOS switch, for example, the size of one unit switch is: NMOS: 15u/0.35u, PMOS: 55u/0.3u. �The total gate area is about 20 um^2, and Cox=10 fF/um^2, so the total parasitic cap is 20*10=200 fF.
The linearity will not satisfy the SFDR performance if the size of switch get smaller.

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