oermens
|
Hi, I want to do layout of some CML gates. Since there are no standard cells for this logic family (or are there?), what is the best way to do the layout? I figure symmetry is important, what else? Should transistors be drawn on a single active, or as they are arranged in schematic (stacked diff pairs)? Would each diff pair need its own guard ring?
My design works in UHF range.
Thanks.
|