sheldon
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Steve,
First question, when you say that is was designed to operate at 125MHz, how did you verify the SINAD at 125MHz?
Next suppose that the front-end, S/H, that the duty cycle is 40%/60% instead of 50%/50%, then effectively it is operating at 156.25MHz instead of 125MHz. That is, instead of 4ns to acquire and 4ns to settle [hold], there are now 3.2ns(4.8ns) to acquire and 4.8ns(3.2ns) to settle. Reducing the amount of time to perform either operation will increase the distortion, due to incomplete settling. When you designed the ADC did you allocate margin for duty cycle variation?
Best Regards,
Sheldon
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