Having lower input common mode means an extended swing at the output before the input transistor goes into triode region.

Bupesh

Assume the input to the data has CM=dx
Assume input to clock has CM=cx

Now if all the gates are at their common-mode, then we get the drain of the clock transistors as having a voltage = dx-vgs
whereas the clock transistors will have Vg=cx

So ideally you'd like clock ones to have cx<dx.

Simulate it. I think you will see extra glitches in your output. But maybe you are okay with it.