Hi

I am trying to simulate switchcap resistors using transient analysis.
The first version i simulate (shown above in the attached picture) is the parasitic sensitive version. The simulation of this version works fine. However, when I try to simulate the parasitic insensitive version(shown below in the attached picture), zero diagonal in Jacobian occurs. It helps to reduce the switch off resistance and increase the switch on resistance but there are still convergence problems and simulations feel somewhat unstable.

I know that this has something to do with a fast charging
of the capacitor which creates large currents and floating nodes but
i don't know what the problem is exactly and how to avoid it. Are
there any ways to solve this and are there any general guide lines
to avoid convergence problems when simulating sc-circuits?

Thanks for the reply

Hi Ken,

Thanks for the reply!

Here is the veriloga model for the switch.
I have removed the terminals Vdd, gnd and
oni which was some old stuff left behind.

module Switch(A, B, On);
inout A;
electrical A;
inout B;
electrical B;
input On;
electrical On;

parameter real R1 = 1;
parameter real Roff = 100G;

parameter real vl_h = 1.2;
parameter real vl_l = 0;

parameter integer trig_edge = 1; //+1 => rising edge, -1 => falling edge

real Rout;

analog begin
 
 @(initial_step) begin
   Rout = Roff;
 end

 @(cross(V(On)-(vl_h-vl_l)/2, trig_edge)) begin
   Rout = R1;
 end

 @(cross(V(On)-(vl_h-vl_l)/2, -trig_edge)) begin
   Rout = Roff;
 end
   
 I(A,B) <+ V(A,B) / Rout;

end

endmodule

I have also attached a picture of the clock signals. From
there it can be observed that the clock phases are a quarter of clock
period wide which will result in a floating capacitor during the time
slot when all switches are open just as you observed. There are
no parasitic capacitances in the switch.

The output log is listed below. At that time I had R1 = 1 and Roff = 10 G. The simulator continues indeed and the waveforms look alright
but I don't know if the error messages are worrying.

***********************************************
Transient Analysis `tran': time = (0 s -> 2 us)
***********************************************
Important parameter values:
   start = 0 s
   outputstart = 0 s
   stop = 2 us
   step = 2 ns
   maxstep = 20 ns
   ic = all
   skipdc = no
   reltol = 100e-06
   abstol(I) = 1 pA
   abstol(V) = 1 uV
   temp = 27 C
   tnom = 27 C
   tempeffects = all
   errpreset = conservative
   method = gear2only
   lteratio = 10
   relref = alllocal
   cmin = 0 F
   gmin = 1 pS

Zero diagonal found in Jacobian at `net076' and `net076'.
Zero diagonal found in Jacobian at `net076' and `net076'.
Zero diagonal found in Jacobian at `net076' and `net076'.
Zero diagonal found in Jacobian at `net076' and `net076'.

Warning from spectre at time = 1 ns during transient analysis `tran'.
   WARNING (SPECTRE-16266): Error requirements were not satisfied because of convergence difficulties.

   tran: time = 64.67 ns    (3.23 %), step = 20 ns           (1 %)

Warning from spectre at time = 125.5 ns during transient analysis `tran'.
   WARNING (SPECTRE-16191): Minimum time step used.  Solution might be in error.
Warning from spectre at time = 125.5 ns during transient analysis `tran'.
   WARNING (SPECTRE-16191): Minimum time step used.  Solution might be in error.

   tran: time = 167.1 ns    (8.35 %), step = 20 ns           (1 %)
   tran: time = 250 ns      (12.5 %), step = 11.47 ns     (574 m%)

Warning from spectre at time = 250.5 ns during transient analysis `tran'.
   WARNING (SPECTRE-16191): Minimum time step used.  Solution might be in error.
Warning from spectre at time = 250.5 ns during transient analysis `tran'.
   WARNING (SPECTRE-16191): Minimum time step used.  Solution might be in error.

   tran: time = 352.1 ns    (17.6 %), step = 20 ns           (1 %)

Warning from spectre at time = 375.5 ns during transient analysis `tran'.
   WARNING (SPECTRE-16191): Minimum time step used.  Solution might be in error.
       Further occurrences of this warning will be suppressed.

   tran: time = 457.1 ns    (22.9 %), step = 20 ns           (1 %)
   tran: time = 562.1 ns    (28.1 %), step = 20 ns           (1 %)
   tran: time = 667.1 ns    (33.4 %), step = 20 ns           (1 %)
   tran: time = 750 ns      (37.5 %), step = 11.47 ns     (574 m%)
   tran: time = 852.1 ns    (42.6 %), step = 20 ns           (1 %)
   tran: time = 957.1 ns    (47.9 %), step = 20 ns           (1 %)
   tran: time = 1.062 us    (53.1 %), step = 20 ns           (1 %)
   tran: time = 1.167 us    (58.4 %), step = 20 ns           (1 %)
   tran: time = 1.25 us     (62.5 %), step = 11.47 ns     (574 m%)
   tran: time = 1.352 us    (67.6 %), step = 20 ns           (1 %)
   tran: time = 1.457 us    (72.9 %), step = 20 ns           (1 %)
   tran: time = 1.562 us    (78.1 %), step = 20 ns           (1 %)
   tran: time = 1.667 us    (83.4 %), step = 20 ns           (1 %)
   tran: time = 1.75 us     (87.5 %), step = 11.47 ns     (574 m%)
   tran: time = 1.852 us    (92.6 %), step = 20 ns           (1 %)
   tran: time = 1.957 us    (97.8 %), step = 20 ns           (1 %)
Number of accepted tran steps =             1954
Intrinsic tran analysis time =              310 ms.
Total time required for tran analysis `tran' was 320 ms.


Warning from spectre.
   WARNING (SPECTRE-6006): 25 warnings suppressed

It would have been nice if you would have translated the error message. You are asking for help and I told you the error message was important. You should have at least indicted which node was net076.

It's funny, I have been answering questions on this forum for years, and it is clear as day that it would be better for everyone if people took more care when they ask their questions. For example, you gave the schematic, but did not give the error message, an error message that specifically identifies where the problem is in the circuit. Doesn't that seem important to you? You also forgot to mention that the simulation actually completed and gave seemingly correct results. That seems like an important detail to me. You also complained about convergence, but there was no issue with convergence in this circuit. All of these things mean that to help you I have to quiz you, which discourages me from answering and if I do answer, significantly slows the response.

Sorry, I digress.

You have presented the simulator with an over-idealized circuit, and it is doing the best it can. Perhaps it is being a bit verbose, but it seems like the result is correct. You can make life a little easier on the simulator if you smoothly change the resistance of the switch by passing Rout through a transition statement. And personally, I would have used an if statement to determine whether the switch was on or off, and only used a single cross function to resolve the threshold crossing if that were important. That eliminates the need for the initial block.

-Ken