A further to Ken's post.
Quote:PSS/PNoise simulation is needed for certain blocks such as the VCO, the frequency divider, and the PFD/CP. You cannot use a simple SPICE noise analysis with these blocks because the noise they produce with a DC operating point is much different from the noise they produce when actually operating properly.
Once you have all the noise contributors you can generally use a simple AC analysis for the phase domain model that is used to combine all the contributions to predict the output noise.
Certain Blocks like CP, you would say, would generate current noise constantly.
But, in Locked State, that noise enters the Loop( Discrete Time Operation of PFD ) for only certain Time Period, which is the reset delay of PFD.
This makes it a sampled operation. Current noise is sampled every T
comparision & is visible to the loop for T
reset only.
Thus, all effects like Noise Folding come into play.
Hence, the need for PSS / PNOISE instead of normal small signal NOISE analysis.
Quote:1) Like Count said that each block in PLL has different beat frequency, should we just use sweeptype=relative for PFD+CP, divider and VCO, and don't care about the fact that each block has different beat frequency?
PLL is a completely non-linear system.
If for eg, you take the VCO. For Ease of Understanding, we can say TF of VCO is A*sin(w*t + Φ). Whatever small signal you apply at a Frequency Δf automatically gets upconverted to Fosc +- Δf due to mixing operation (sine multiplication) of VCO.
Hence, the frequency of a signal at LF o/p gets upconverted around Fosc.
If we develop a PLL Model with sine & cosine TFs, it would become too complex & diff. to understand & solve. Hence, we develop a small signal Phase Domain Model in which we take Noise contributions around each block's Periodic Steady-State Operating Frequency(Beat Freq.) & a small signal gain of conversion around It's Beat Frequency. & then we can model each block as a normal tf without any periodic functions like sine or cosine. Makes our lives easier.
Key Point Being, we already took care of Diff. Beat Freqs. & up/down conversion when we take into acc. noise/signal contribution at Different & appropriate Beat Freqs. from diff. blocks. Quote:2) Assume we using phase domain noise model for the PLL. I know we should use pnoise+jitter to get phase noise of VCO (dBc/Hz). Should we also use pnoise+jitter for divider and PFD+CP? If so, I have two pussles:
You can use normal Pnoise/Pnoise Modulated analysis for VCO.
For Driven ckts. like PFD/CP & Dividers, you need to perform time-strobed Pnoise.
Quote: a) for divider if jitter feature is used, should we set the stop frequency of sweeprange to half beat frequency or just set it to the offset frequency range of interest and don't care about the noise folding?
Always, All Noise Folding Effects should be considered. keep Max. Freq. around 50x the OutPut Freq.
Quote:b) for PFD+CP if jitter feature is used, how can we set the threshold value?
Which Threshold ?
Probably, one of my Length-iest posts. :P
--
Mayank.