Hello all,

I'm using Cadence IUS tool (Version 9.2) to simulate the top level of a device.
It includes digital written in verilog and netlist of the alalog design. Also several verilogams files were written and should be used as modules in the analog design.

I'm facing a problem includeing these modules in the flow.

What I did is the following:

1. Declared the module in the amsd block inside the amscf.scs file: portmap module=BU140J_mod reffile="/sim/TLK110/AMS_Eyal/Release2/SRCA/BU140J_mod.vams"
config cell=BU140J_mod use = hdl

2. Wrote the path and file name in the run script:
/sim/TLK110/AMS_Eyal/Release2/SRCA/BU140J_mod.vams

3. Wrote a subckt definition in the netlist:
subckt BU140J_mod A VDD VSS Y
end subckt

When I run the run script with these definitions I get an error pointing to this module:
      ERROR: Cannot find instance 'BU140J_mod' in the AMSD control block file './amscf_try.scs'. Verify that the instance exist and that you have specified it properly.


I'm not sure I declare the vams module properly.

Can anyone please help me with this issue?
Did I miss something with the declaration of the module?

Thanks in advance,

Eyal