vivkr
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I have also seen:
1. "digital" nonoverlap where the system clock is much faster than the ADC clock, and the N.O. is thus chosen as 1 clock phase or so; not as bad as you might think, especially since there are practically no variations in the N.O.
2. On a similar note, but for higher speed systems which had a DLL on-chip, one could similarly generate a N.O. Might look a little riskier if the N.O. phases are not routed symmetrically, but that's a risk you always have with every method.
Vivek
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