Hi,

Several grad students in my department do research on PPLs and frequency synthesizers and we're looking for a tool which can accurately predict their phase noise. We couldn't get Cadence PLL Workshop since the IP is not available for academic users, so we're looking at GoldenGate PLL Simulator. Has anyone used this tool before? Have you compared the results with actual measurement? How long is the simulation time, since it uses transistor level models unlike Cadence PLL workshop which uses VerilogA.

Thanks.