Dear all,

I have written phase domain modells for my PLL according to the "Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers" paper by Ken. I have created a veriloga and symbol cell view for each of the modells. I have then assembled them together in a schematic and simulated it with Spectre. I can simulate the ac behaviour and the phase noise of the PLL.

I was wondering whether a transient simulation of the lock-in behaviour of the PLL is possible. I guess I need to change the reference oscillator with another source. Can anyone please clarify if the transient simulation is possible and if yes, how it is possible.

Thanks,
Thomas

There is a way to write phase domain models of the PFD and VCO that let you quickly simulate acquisition transients. The Cadence SpectreRF user's guide has a section called "Introduction to the pllLib" that explains the model pretty well. You can also find a few charts on it in the tutorial given at the 2001 BMAS (see link below). The trick is to move the VCO integrator into the PFD and then make that integrator resettable. I've had pretty good success with this method. I've also used it with time domain noise sources and CP nonlinearities to quantify sigma delta noise folding.

http://www.bmas-conf.org/2001/index.html