Quote:Is it because the PLL LPF BW they used are <<1M Hz?
especially in freq synthesizer..
For Integer PLLs, toi keep a Loop BW of 1MHz, assumnig you want to design with Gardener's principle, your Fref or Fcomparison should be more than 10MHz ateast.
XOs generally come with haphazard frequencies like 9.6 MHz / 13 MHz, etc. in which case you need to divide down the reference freq. to an integer division of output freq. This reduces your Fref & hence you max PL BW spec.
For fractional PLLs, to control the S-D noise from dominating the output, PLL BW has to be kept low.
Freq Synthesizers can be based on both Integer as well as Fractional PLLs. SO their BW is genearlly low, but it can go above 1 MHz.
This should not be the only explanation to your original question.
Gotta think a bit more. Maybe on the lines that Flicker Noise causes Random Walk in PLLs.
--
Mayank