Hi

i am designing an inductive Powersupply to do my diploma thesis. For generating the testbench and certain moduls currently not buildiable with our current pdk (certain primitives arn't in the pdk yet) iam using verilog-AMS.

Iam writing the verilog modules in virtuoso and generate symbols to use them in schematics. After making the config view NCSim starts.
In the Testbench iam combining verliog-ams moduls, i built with primitives from our pdk (mainliny MOSFETS),with the verilogams modules to do the simulation in ncsim.


this works fine for the moment, but what i cant find is a way to sweep a certain variable.

Like the Voltage of a Verilog-DC-Voltage supply or a parameter of a mosfet like the width.

Is it done like in ADE, simple declaring a variable in the cdf parameters or how?