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mowiehowie

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Mismatch problems with bandgap voltage reference
Jun 8^th, 2010, 12:23pm

So, I got to work with this bandgap circuit, and it needs an amplifier. I built a simple one, two-stage amplifier (p-diff followed by a common-source), and it seems it's ok through my testbenchs (PVT, corners). Its gain is around 100 dB (i was kinda surprised with that) with good phase margin, and its offset is around 5mV (testbench performed with monte-carlo 3sigma).

When I attach this amplifier to the bandgap circuit and perform a MC to see how mismatch (lots and devs) affects the output voltage, for some MC runs the output is nearly zero or even zero.

Well, just to let you know, it doesn't seem to be an offset problem because I added an ideal opamp with a 5mV offset varying with a gauss distribution (+/- 3sigma) and the results are pretty good.
Also, I'm not using any start-up circuit right now, I'm using a .nodeset condition.

Any ideas/comments/suggestions ?

Thank you.

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bandgap.jpeg

« Last Edit: Jun 08^th, 2010, 9:23pm by mowiehowie »

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AnalogDE Senior Member Offline Posts: 137	Re: Mismatch problems with bandgap voltage reference Reply #1 - Jun 8^th, 2010, 5:06pm I would just throw in the startup circuit. You're going to need it eventually anyway.
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Mayank

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Re: Mismatch problems with bandgap voltage reference
Reply #2 - Jun 8^th, 2010, 8:56pm

Quote:

Perhaps, when I attach this amplifier to the bandgap circuit and perform a MC to see how mismatch (lots and devs) affects the output voltage, for some MC runs the output is nearly zero or even zero.

BGR performing correctly with an ideal opamp while functioning incorrectly with a practical one most prob. indicates Loop Stability Problem.

Also, if possible, find out the values of other parameters in the particular run which gave VREF=0 & simulate that particular case in a separate test-bench. See if you can find out the problem then.

--
Mayank.

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mowiehowie

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Re: Mismatch problems with bandgap voltage reference
Reply #3 - Jun 10^th, 2010, 5:53pm

tough work....
what are the main issues regarding stability, looking at that picture ?
i cant find out whats going on with my circuit..
well.. it was unstable, so i made those PMOS narrower and longer, and the pmoses at the RIGHT side are 1.5 times longer than the PMOS on the right. it seems the instability issue is gone, 'cause the output is not oscillating anymore in transient simulations. i think by lowering the current at the right side, that diode will have a smaller gm, and therefore, the impedance on that branch will be higher, making the gain more negative, and therefore the overall feedback. it's just a guess though.

anyway, there are some discrepancies between the .tran analysis and the .dc sweep analysis. my circuit is supposed to start at vdd = 2.7. Well, it doesnt start for every 2.7V=vdd in .dc sweep analysis, sometimes it doesnt even start.
but running transient analysis with vdd=2.7 (MC dev, 1024 runs), its working for every run ! the circuit's started for every run.

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« Last Edit: Jun 11^th, 2010, 7:08am by mowiehowie »

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Mayank

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Re: Mismatch problems with bandgap voltage reference
Reply #4 - Jun 10^th, 2010, 8:59pm

Quote:

well.. it was unstable, so i made those PMOS narrower and longer, and the pmoses at the left side are 1.5 times longer than the PMOS on the right. it seems the instability issue is gone, 'cause the output is not oscillating anymore in transient simulations. i think by lowering the current at the right side, that diode will have a smaller gm, and therefore, the impedance on that branch will be higher, making the gain more negative, and therefore the overall feedback. it's just a guess though.

I would suggest you to keep the -ve FB loop gain atleast twice the +ve FB loop gain.
Do the small signal analysis & ensure this point.

Quote:

anyway, there are some discrepancies between the .tran analysis and the .dc sweep analysis. my circuit is supposed to start at vdd = 2.7. Well, it doesnt start for every 2.7V=vdd in .dc sweep analysis, sometimes it doesnt even start.
but running transient analysis with vdd=2.7 (MC dev, 1024 runs), its working for every run ! the circuit's started for every run.

Maybe some DC convergence issues. Use gramp or some damped psuedo-tran convergence methods in DC analysis.

--
Mayank

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newic Senior Member Offline Posts: 138	Re: Mismatch problems with bandgap voltage reference Reply #5 - Jun 10^th, 2010, 10:05pm Did you check the phase margin of the opamp. High gain opamps tend to have stability issue.
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Mayank Community Fellow Offline Posts: 334	Re: Mismatch problems with bandgap voltage reference Reply #6 - Jun 11^th, 2010, 12:05am Quote: Did you check the phase margin of the opamp. Check the PM of the whole system (which includes both +ve & -ve FB loops) by breaking it at a common node, eg, the Opamp output. & giving the test ac voltage at the pmos I/Ps.
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mowiehowie Junior Member Offline Posts: 26	Re: Mismatch problems with bandgap voltage reference Reply #7 - Jun 11^th, 2010, 7:28am my opamp has a good PM, like 85~90... its compensated with a capacitor and a resistance. 'bout the dc convergence issues, i tried to use the clamp option, same results. i use eldo. well.. if anyone has any tips about this simulation issues, i'd be thankful. thanks everyone.
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rfcooltools.com

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Re: Mismatch problems with bandgap voltage reference
Reply #8 - Jun 15^th, 2010, 12:18pm

Three suggestions

1. Band gaps like this have two solutions when the input +-ve are equal the first is when the output is bandgap and the second is when the input are both zero. so a start up condition must be managed.
2. The opamp PM is only part of the loop, the MOS device at the top is the other part of the loop and the transfer function from the input of these pmos devices to a differential voltage is not with out some kind of pole (and usually reduces overall gain significantly).
3. Your opamp might be starting up in a no gain condition thus the loop is open and no bandgap

Suggestions add two pmos devices in parallel to supply a current to both branches . This current does not have to be accurate it just has to always be less than the minimum operating current plus some margin.

Run a loop stability with the entire circuit a good place to break the loop is between the opamp output and the pmos input.

http://rfcooltools.com

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