Quote:well.. it was unstable, so i made those PMOS narrower and longer, and the pmoses at the left side are 1.5 times longer than the PMOS on the right. it seems the instability issue is gone, 'cause the output is not oscillating anymore in transient simulations. i think by lowering the current at the right side, that diode will have a smaller gm, and therefore, the impedance on that branch will be higher, making the gain more negative, and therefore the overall feedback. it's just a guess though.
I would suggest you to keep the -ve FB loop gain atleast twice the +ve FB loop gain.
Do the small signal analysis & ensure this point.
Quote:anyway, there are some discrepancies between the .tran analysis and the .dc sweep analysis. my circuit is supposed to start at vdd = 2.7. Well, it doesnt start for every 2.7V=vdd in .dc sweep analysis, sometimes it doesnt even start.
but running transient analysis with vdd=2.7 (MC dev, 1024 runs), its working for every run ! the circuit's started for every run.
Maybe some DC convergence issues. Use gramp or some damped psuedo-tran convergence methods in DC analysis.
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Mayank