Hi all,

I am relativly new in the field of mixed-signal asic design and currently
working on my master thesis.

In my project I am working with the Hit-Kit 4.00 (austria microsystems) and use the c35 technology.

After synthesized my vhdl code with the encounter rtl compiler, i also
generated an sdf file with the command "write_sdf". My next task is to do an post synthesys simulation with the generated verilog gate level netlist with some analog circuits. For this reason i imported the verilog
file in cadence virtuoso and referenced the c35_CORELIB.v file wich comes frome the Hit-Kit vendor.

After doing successful simulations without backanotated the sdf file I referenced the sdf file in the ams simulator options with an sdf command file.

But after starting the simulation the elaborator produced this error:

ncelab: *W,SDFNET: Failed Attempt to annotate to non-existent timing check (REMOVAL (posedge RN) (posedge C) ()) of instance ... DFEC1

for nearly all instances.  :'(

I have no idea how to fix it. I only think it has something to do with maybe different element discriptions of the standard cells in the c35_CORELIB.v and de SDF file.

It would be great if somebody has and idea or solution how to solve my problems.

Thanks in advance and best regards,

Mike