Quote:It is a new process, designers told me automatic post layout simulation is not yet possible. Parasitics have to be included by hand, so there is at the moment only the model of the transmission lines in series with its resistance, no routing capacitances included.
Which transmission lines are you talking about ?
Are you including any such T-line models in your schematic ??
Quote:I added in the Pre-Layout a inductance in series to Rc and the output frequency increase as in the Post-Layout simulation. Designers told me its a shock inductance but I asked google and found nothing that explain my problem. (Only for understanding the designers are french and their english is not so good, so I have to find out by myself.)
Havent heard of any shock inductance arising at source node, unless you deliberately place one.