Hi,

I am trying to get to grips with wreal modelling in verilog ams, so please forgive any 'stupid' questions.

I am trying to substitute verilog ams blocks into a top level schematic, using Cadence's Hierarchy Editor and ADE simulation environment. I have a very simple model of a transmission gate, which I've coded as follows:

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//Verilog-AMS HDL for "adcLib", "tx_gate" "verilogams"

`include "constants.vams"
`include "disciplines.vams"

module tx_gate ( out, enable, in, not_enable );

 input wreal in;
 input enable;
 input not_enable;
 output wreal out;
 real out_wire ;
 
 always@(enable or not_enable)
   begin
     if (enable)
           out_wire = in;
     else
           out_wire = `wrealZState;
   end
 
 assign out = out_wire;
 
endmodule
-------------------------

but it doesn't work, there is no output in either state.

What have I done wrong?
Are the port declarations and useage correct?
can I use `wrealstateZ like this?

Any enlightment would be appreciated!

Thank you,

E