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supermoment

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Posts: 167

adc verilogA errors!
Jun 25^th, 2010, 1:18am

The code was copied from designers-guide.org. So it should be correct.

I got several errors about the code and i do not know how to solve it.
I am using IC5141, mmsim61.

The errors i got:
Line 36
"for(i = bits-1; i >= 0; i = i-1 )<<--? �begin"
Line 36
Error: In for-loop control, genvar expression can only consists of
�integer constant or other unrolled genvar variables expression.

Line38
�"result[i]<<--? �= vdd;"
�Error: Genvar variable `i' is referenced within incorrect for-loop.
Line41
�"result[i]<<--? �= 0.0;"
....
many more

Sound like those errors occurs whenever i use [i] or i

Is it my verilogA compiler too old? I am not sure how to check the version.

Code:

`include "constants.vams"
`include "disciplines.vams"

module adc (out, in, clk);
	 �parameter integer bits = 8 from [1:24];
	 �parameter real fullscale = 1.0;
	 �parameter real td = 0;
	 �parameter real tt = 0;
	 �parameter real vdd = 5.0;
	 �parameter real thresh = vdd/2;
	 �// resolution (bits)
	 �// input range is from 0 to fullscale (V)
	 �// delay from clock edge to output (s)
	 �// transition time of output (s)
	 �// voltage level of logic 1 (V)
	 �// logic threshold level (V)

	 �parameter integer dir = 1 from [-1:1] exclude 0;
	 �// 1 for rising edges, 1 for falling

	 �input in, clk;
	 �output [0:bits-1] out;
	 �voltage in, clk;
	 �voltage [0:bits-1] out;
	 �real sample, midpoint;
	 �integer result[0:bits-1];

	 �genvar i;

	 �analog begin
		 � �@(cross(V(clk)-thresh, +1) or initial_step) begin
				sample = V(in);
				midpoint = fullscale/2.0;
				for(i = bits-1; i >= 0; i = i-1 ) begin
					 �if(sample > midpoint) begin
						 � �result[i] = vdd;
						 � �sample = sample - �midpoint;
					 �end else begin
						 � �result[i] = 0.0;
					 �end
					 �sample = 2.0*sample;
				end
		 � �end

		 � �for (i = 0; i < bits; i = i + 1) begin
				V(out[i]) <+ transition(result[i], td, tt);
		 � �end
	 �end
endmodule

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Marq Kole

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Hmmm. That's
weird...

Posts: 122
Eindhoven, The Netherlands

Re: adc verilogA errors!
Reply #1 - Jun 25^th, 2010, 7:17am

I would suggest using a later version of Cadence MMSIM, version 7.2 or later preferably. Lately Cadence have made some changes in the supported syntax for analog for loops and the use of genvars. Actually the restrictions they apply to array indexes are completely unnecessary and not supported by anything in the standard.

Cheers,
Marq

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supermoment Senior Member Offline Posts: 167	Re: adc verilogA errors! Reply #2 - Jun 25^th, 2010, 8:35am do you have any workaround or methods other than using mmsim72??
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pancho_hideboo

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Posts: 1424
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Re: adc verilogA errors!
Reply #3 - Jun 25^th, 2010, 9:04am

supermoment wrote on Jun 25^th, 2010, 8:35am:

do you have any workaround or methods other than using mmsim72??

Try to modify like following, although I don't know vendor's name of which you use simulator.
Quote:

`include "constants.vams"
`include "disciplines.vams"

`define �Bits � � 8

module adc (out, in, clk);
�//parameter integer bits = 8 from [1:24];
�parameter real fullscale = 1.0;
�parameter real td = 0;
�parameter real tt = 0;
�parameter real vdd = 5.0;
�parameter real thresh = vdd/2;
�// resolution (bits)
�// input range is from 0 to fullscale (V)
�// delay from clock edge to output (s)
�// transition time of output (s)
�// voltage level of logic 1 (V)
�// logic threshold level (V)

�parameter integer dir = 1 from [-1:1] exclude 0;
�// 1 for rising edges, 1 for falling

�input in, clk;
�output [0:`Bits-1] out;
�voltage in, clk;
�voltage [0:`Bits-1] out;
�real sample, midpoint;
�integer result[0:`Bits-1];

�genvar i;

�analog begin
� �@(cross(V(clk)-thresh, +1) or initial_step) begin
sample = V(in);
midpoint = fullscale/2.0;
for(i = `Bits-1; i >= 0; i = i-1 ) begin
�if(sample > midpoint) begin
� �result[i] = vdd;
� �sample = sample - �midpoint;
�end else begin
� �result[i] = 0.0;
�end
�sample = 2.0*sample;
end
� �end

� �for (i = 0; i < `Bits; i = i + 1) begin
V(out[i]) <+ transition(result[i], td, tt);
� �end
�end
endmodule

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supermoment

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Posts: 167

Re: adc verilogA errors!
Reply #4 - Jun 25^th, 2010, 11:25pm

sorry, i �i posted the old version one.
The new version had fixed the "Bits" problem before the 1st post.

Code:

`include "constants.vams"
`include "disciplines.vams"

module adc (out, in, clk);
	 �parameter integer bits = 8 from [1:24];
	 �parameter real fullscale = 1.0;
	 �parameter real td = 0;
	 �parameter real tt = 0;
	 �parameter real vdd = 5.0;
	 �parameter real thresh = vdd/2;
	 �// resolution (bits)
	 �// input range is from 0 to fullscale (V)
	 �// delay from clock edge to output (s)
	 �// transition time of output (s)
	 �// voltage level of logic 1 (V)
	 �// logic threshold level (V)

	 �parameter integer dir = 1 from [-1:1] exclude 0;
	 �// 1 for rising edges, 1 for falling

	 �input in, clk;
	 �output [0:bits-1] out;
	 �voltage in, clk;
	 �voltage [0:bits-1] out;
	 �real sample, midpoint;
	 �integer result[0:bits-1];

	 �genvar i;

	 �analog begin
		 � �@(cross(V(clk)-thresh, +1) or initial_step) begin
				sample = V(in);
				midpoint = fullscale/2.0;
				for(i = bits-1; i >= 0; i = i-1 ) begin
					 �if(sample > midpoint) begin
						 � �result[i] = vdd;
						 � �sample = sample - �midpoint;
					 �end else begin
						 � �result[i] = 0.0;
					 �end
					 �sample = 2.0*sample;
				end
		 � �end

		 � �for (i = 0; i < bits; i = i + 1) begin
				V(out[i]) <+ transition(result[i], td, tt);
		 � �end
	 �end
endmodule

I got the same error message as in the first post.

It is related to the loop with "i"

I am using Cadence mmsim61.

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supermoment

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Posts: 167

Re: adc verilogA errors!
Reply #5 - Jun 26^th, 2010, 12:40am

I have tried the method, but it does not work as well

line 6: "'<<- �-? define Bits 8"

line 26: �"output [0:'Bits<<--? -1] out;"

I am new in VerilogA.
Sounds like I could not use 'define Bits 8

I also tried the to use generate i;
in both cases ( with 'define Bits 8 or parameter interger Bits = 8 from [1:24];)
But it does not work at all... :D

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supermoment Senior Member Offline Posts: 167	Re: adc verilogA errors! Reply #6 - Jun 26^th, 2010, 1:01am Thanks a lot. it works eventually.. The mistake i made was using ' instead of ` I learned the lesson.
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pancho_hideboo Senior Fellow Offline Posts: 1424 Real Homeless	Re: adc verilogA errors! Reply #7 - Jun 26^th, 2010, 1:16am supermoment wrote on Jun 26^th, 2010, 1:01am: The mistake i made was using ' instead of `. Simply you did same mistakes as the following. http://www.designers-guide.org/Forum/YaBB.pl?num=1264401024/1#1 All threads after following are unnecessary. http://www.designers-guide.org/Forum/YaBB.pl?num=1277453893/3#3
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