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Phase Margin/Stability check (Read 1447 times)
turbo
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Phase Margin/Stability check
Jun 18th, 2010, 7:23am
 
Hi,

Could you anyone please share his/her knowledge on the following:

How to verify and calculate the phase margin/stability of a fully balanced two stage OTA-C configuration with output connected as feedback to the negative input and Vin to the positive input.

I'm using Cadence Analog Artist!

Thanks,
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turbo
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Re: Phase Margin/Stability check
Reply #1 - Jun 18th, 2010, 7:32am
 
I should be measuring the open loop gain, but not sure how given the following.

OTA inputs:

V+ = V input
V- = Vout (via feedback)
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sheldon
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Re: Phase Margin/Stability check
Reply #2 - Jun 18th, 2010, 5:37pm
 
Turbo,

  In order to measure the loop gain and phase margin use stability
analysis. It is stb in the ADE Analysis menu. For the details of the
analysis, please see the following reference for the details of the
analysis,

   http://www.kenkundert.com/docs/cd2001-01.pdf

You will need to add a probe to testbench for stability analysis.

                                                             Best Regards,

                                                                Art Schaldenbrand
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love_analog
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Re: Phase Margin/Stability check
Reply #3 - Aug 7th, 2010, 1:33pm
 
Some people may not have stb.

One way for those folks is to open the loop and then measure stability. There are many ways to open the loop.

Try googling middlebrook's stability analysis.

I don't know about fully differential but a single ended one in which you put an inductor in feedback with cap coupled source works. I think you can do the same for fully diff one.
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sheldon
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Re: Phase Margin/Stability check
Reply #4 - Aug 7th, 2010, 7:14pm
 
Turbo,

   In case you don't have access to stb analysis, please review
"The Designer's Guide to SPICE and Spectre", section 3.4.1.
Several approaches to stability analysis discussed including:
1) Using VCVS to set the feedback and directly measuring the loop
   gain.
2) Middlebrook's method
3) Two-port method    
All these methodologies will allow you to perform stability analysis,
however, they will also require some post-processing. If you
do use inductor/capacitor based testbench, you should also review
the DG to SPICE and Spectre. There are some limitations with this
approach and they are discussed in the book.

                                                          Best Regards,

                                                             Sheldon
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Frank Wiedmann
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Re: Phase Margin/Stability check
Reply #5 - Aug 9th, 2010, 2:38am
 
For loop gain simulation of a symmetrical differential circuit, see http://www.designers-guide.org/Forum/YaBB.pl?num=1190707743.

For an implementation of the stb analysis method in the free LTspice simulator, see my webpage http://sites.google.com/site/frankwiedmann/loopgain.
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